1. Field of the Invention
The present invention relates to integrated circuit input/output structures. More specifically, the invention relates to protecting an integrated circuit from electrostatic discharge using a low-capacitance input/output and electrostatic discharge circuit.
2. Background
Integrated circuits are well known in the art. An integrated circuit should be handled with care. As for any complementary Metal Oxide Semiconductor (CMOS) integrated circuits, they can be damaged by Electrostatic Discharge (ESD). The gate oxide part of the CMOS chip may be very thin and can be damaged by electrostatic discharge (voltage established by “static” electricity between the gate oxide and the drain or source inside the integrated circuit). An electrostatic discharge (ESD) in an integrated circuit may result from static electricity build-up caused in the handling of a device, for example friction of the device against packaging material or from static electricity build-up on a person who is not properly grounded or protected against static build-up.
An electrostatic discharge through an integrated circuit can cause a relatively high current to flow through the device. If the current flows through a small feature of the device, the resulting heat could cause the feature to melt, explode, or otherwise fail or be damaged. An integrated circuit designer when designing a chip should take into account all possible ESD current paths within the device and provide alternative paths that will allow current to flow without damaging a feature of the device. An effective discharge path will have a relatively large structure that will not be damaged by the discharged current and a relatively low resistance so that current will easily flow along the designated path.
A traditional structure that is well suited for handling ESD currents is a transistor used in an input/output circuit for an integrated circuit that contains a doped well under all components of the transistor. FIG. 1 is a simple diagram illustrating the structure of transistor 100. As shown in FIG. 1, the source and drain regions are N+ structures 102, while the doped well 104 is a P well. This structure is well suited to ESD currents because of the large size of the transistor 100 and the large area of the junction between the center N+ region 102 and P-well 104 regions. This large junction area, however, leads to a large capacitance, which slows down the performance of the device. As is well known to those of ordinary skill in the art, the higher the doping of the P-well 104, the larger the capacitance of the junction.
Thus, when designing an ESD structure, the designer attempts to isolate all possible discharge currents and direct them through components of the device that will not be damaged by them, e.g., diverting them through the substrate to a ground potential. The use of input/output circuits as ESD protection circuits is known in the art.
FIGS. 2 and 3 illustrate known ESD protection circuits for an integrated circuit device as further decribed in U.S. Pat. No. 6,365,941 to Rhee. FIG. 2 shows a simplified schematic diagram of a conventional ESD circuit 120. ESD circuit 120 comprises a diode 122 coupled between an input/output pad 124 and grounded semiconductor substrate 126. In this conventional ESD circuit, a P-type anode and an N-type cathode of diode 122 are coupled to grounded semiconductor substrate 126 and input/output (I/O) pad 124, respectively. Also, the I/O pad 124 is coupled to an internal circuit 128 such as an FPGA or other integrated circuit. In this case, a reverse breakdown voltage of the diode 122 must be higher than an operating voltage of internal circuit 128. Therefore, if a voltage lower that the operating voltage of internal circuit 128 and higher than a ground voltage is applied to pad 124, the internal circuit operates normally. If, however, a voltage higher than the operating voltage of internal circuit 128 or a negative voltage is applied to pad 124, it is by-passed through diode 122. Accordingly, internal circuit 128 is protected from excessive currents.
FIG. 3 is a vertical sectional view of a structure in which the ESD circuit 120 in FIG. 2 is implemented in a semiconductor substrate. Referring to FIG. 3, field isolation regions 152 defining active areas are formed in a semiconductor substrate 154. In one example, a P-type semiconductor substrate 154 is employed and N-type impurity region is formed in one of the active areas between isolation regions 152. The N-type impurity region consists of a heavily doped N-type impurity region 158 surrounded by a lightly doped impurity region 156. The N-type impurity region 156 is formed in the same process step as the source-drain regions of high voltage NMOS transistors. In addition, an impurity region doped with impurities of the same conductivity as that of the semiconductor substrate 154 (a P-type impurity region 160) is formed in an active area adjacent to the N-type impurity region. The P-type impurity region 160 serves as a pick-up area for applying bias voltage, i.e., a ground potential, to the semiconductor substrate 154. The isolation layers 152 and the active regions are covered by an interlayer dielectric film. The heavily doped N-type impurity region 156 is connected to I/O pad electrode 162 passing through a predetermined area of the interlayer dielectric film 164. Thus, the N-type impurity region 156 and the semiconductor substrate 154 respectively form an N-type cathode and a P-type anode of the diode 122 shown in FIG. 2.
The characteristics of the ESD circuit of FIG. 2 are directly affected by the junction area of the diode 122. As the area where the N-type impurity region 158 and the semiconductor substrate 154 contact each other is increased, the electrostatic discharge characteristics, the ESD voltage the device is capable of withstanding, increase. However, the integration density of a semiconductor device employing these ESD structures is relatively reduced.
Therefore, in a conventional ESD circuit of a semiconductor device, it is desired to improve the electrostatic discharge characteristics of the ESD circuit without rendering the integration density of the semiconductor device reduced.
FIGS. 4 and 5 illustrate another known signal input/ESD protection circuit. As illustrated in FIG. 4, ESD protection circuit 200 comprises a transistor 202 and a Zener diode 204 rather than a simple junction diode to protect internal circuit 206 against ESD circuits. In this prior art embodiment, the transistor is not activated unless the voltage on pad 208 exceeds the internal circuit's operation voltage, in which case the transistor is activated and the current is discharged to ground, through transistor 202 and the Zener diode 204. FIG. 5 shows a vertical sectional view 250 of the ESD protection circuit 200 shown schematically in FIG. 4.
Hence, what is needed is an improved transistor junction structure for use in an integrated circuit I/O structure. An I/O structure receives signals from an external circuit and inputs them into an internal circuit of the device, or receives signals form the device and outputs them to an external circuit. There is also a need for an I/O structure that can also serve as the electrostatic discharge protection circuit. Alternatively, a separate electrostatic discharge protection circuit may be used.